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tm december 2006 fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 fin12ac serdes? low-voltage 12-bit bi-directional serializer/deserializer with multiple frequency ranges features low power consumption fairchild proprietary low-power ctl interface lvcmos parallel i/o interface: ? 2ma source / sink current ? over-voltage tolerant control signals parallel i/o power supply (v ddp ) range between 1.65v and 3.6v analog power supply range of 2.5v to 3.05v multi-mode operation allows for a single device to operate as serializer or deserializer internal pll with no external components standby power-down mode support small footprint packaging: ? 32-terminal mlp and 42-ball bga built-in differential termination supports external ckref frequencies; 5mhz to 40mhz serialized data rate up to 560mb/s voltage translation from 1.65v to 3.6v applications microcontroller or pixel interfaces image sensors small displays: lcd, cell phone, digital camera, portable gaming, printer, pda, video camera, automotive description the fin12ac is a 12-bit serializer capable of running a parallel frequency range between 5mhz and 40mhz. the frequency range is selected by the s1 and s2 con- trol signals. the bi-directional data flow is controlled through use of a direction (diri) control pin. the devices can be configured to operate in a unidirectional mode only by hardwiring the diri pin. an internal phase- locked loop (pll) generates the required bit clock fre- quency for transfer across the serial link. options exist for dual or single pll operation, dependent upon system operational parameters. the device has been designed for low power operation and utilizes fairchild proprietary low-power control current transistor logic (ctl) inter- face. the device also supports an ultra low power power- down mode for conserving power in battery-operated applications. ordering information serdes tm is a trademark of fairchild semiconductor corporation. part number package pb-free operating temperature range packing method fin12acgfx 42-ball ultra small scale ball grid array (uss-bga), jedec mo-195, 3.5mm wide yes -30c to +70c tape and reel fin12acmlx 32-terminal molded leadless package (mlp), quad, jedec mo-220, 5mm square yes -30c to +70c tape and reel
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 2 functional block diagram figure 1. fin12ac block diagram connection diagrams figure 2. terminal and pin assignments ckref pllx_sel cks0+ cksi+ + - + - + - + - cksi- cksint diri_int cksint diri_int dso+/dsi- serializer control word ck generator freq control direction control power down control control logic 0 i i 0 word boundary generator serializer deserializer deserializer control pll register register dso-/dsi+ 100 gated termination 100 gated termination diro cks0- ckp s1 s2 diri strobe dp[1:12] i 0 1 2 3 4 5 6 7 8 dp[4] dp[5] dp[6] v ddp ckp dp[7] dp[8] dp[9] 24 23 22 21 20 19 18 17 ckso+ ckso- dso+/dsi- dso-/dsi+ cksi- cksi+ diri v dds 9 10 11 12 13 14 15 16 dp[10] dp[11] dp[12] n/c pllx_sel s2 s1 v dda 32 31 30 29 28 27 26 25 dp[3] dp[2] dp[1] n/c n/c strobe ckref diro terminal assignments for mlp (top view) pin assignments for bga (top view) 1 2 3 4 5 6 a b c d e f g
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 3 terminal descript ions for mlp notes : 1. the dso/dsi serial port pins have been arranged such that if one device is rotated 180 with respect to the other device, the serial connections properly a ligns without the need for any traces or cable signals to cross. other layout orientations may require that traces or cables cross. pin assignments for bga pin assignments pin name i/o type number of terminals description of signals dp[1:12] i/o 12 lvcmos parallel i/o, direction controlled by diri pin ckref in 1 lvcmos clock input and pll reference strobe in 1 lvcmos strobe signal for latching data into the serializer ckp out 1 lvcmos word clock output. this signal is the regenerated strobe signal dso+ / dsi- dso- / dsi+ diff-i/o 2 ctl differential serial i/o data signals (1) dso: refers to output signal pair dsi: refers to input signal pair dso(i)+: positive signal of dso(i) pair dso(i)-: negative signal of dso(i) pair cksi+ / cksi- diff-in 2 ctl differential deserializer input bit clock cksi: refers to signal pair cksi+: positive signal of cksi pair cksi-: negative signal of cksi pair ckso+ / ckso- diff-out 2 ctl differential deserializer output bit clock ckso: refers to signal pair ckso+: positi ve signal of ckso pair ckso-: negative signal of ckso pair s1 in 1 used to define frequency range for the refclock, ckref. s2 in 1 pllx_sel in 1 used to define pll multiplication mode. pllx_sel = 0 multiplication factor 7-1/3x pllx_sel = 1 multiplication factor 7x diri in 1 lvcmos control input. used to control direction of data flow: diri = ?1? serializer diri = ?0? deserializer diro out 1 lvcmos output, inversion of diri v ddp supply 1 power supply for parallel i/o and translation circuitry v dds supply 1 power supply for core and serial i/o v dda supply 1 power supply for analog pll circuitry gnd supply 0 use bottom ground plane for ground signals 1234 5 6 a dp4 dp2 n/c n/c n/c ckref b dp6 dp5 dp1 n/c strobe diro c ckp n/c dp3 n/c ckso+ ckso- dn/c dp7 v ddp gnd dso-/dsi+ dso+/dsi- e dp8 dp9 gnd v dds cksi+ cksi- f dp10 dp11 n/c v dda n/c diri g dp12 n/c n/c pllx_sel s2 s1 n/c = no connect
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 4 control logic circuitry the fin12ac has the ability to be used as a 12-bit seri- alizer or a 12-bit deserializer. terminals s1 and s2 must be set to accommodate the clock reference input fre- quency range of the serializer. table 1 shows the termi- nal programming of these options based on the s1 and s2 control terminals. the diri terminal controls whether the device is the serializer or a deserializer. when diri is asserted low, the device is configured as a deserializer. when the diri terminal is asserted high, the device is configured as a serializer. changing the state on the diri signal reverses the dire ction of the i/o signals and generates the opposite state signal on diro . for unidi- rectional operation, the diri terminal should be hard- wired to the high or low state and the diro terminal should be left floating. for bi-directional operation, the diri of the master device is driven by the system and the diro signal of the master is used to drive the diri of the slave device. pll multiplier the multiply select pin pllx_sel determines whether the pll multiplication factor is 7 times the ckref fre- quency or 7-1/3 times the ckref frequency. overclock- ing the pll increases the range of spread spectrum on the ckref input clock that can be tolerated. both of the pll multiplier modes can work with a non- spread spectrum clock. when operating with the stan- dard 7x multiplier and operating in a ckref = strobe mode, the serialized word is 14 data bits long. each deserializer output period has the same period of the strobe signal. when operating in the overclocking mode, the average deserializer period is the same as the strobe signal. the individual periods vary between 14 and 16 data bits long. the pattern repeats every three cycles with two 14-bit cycles, followed by a third 16-bit cycle. the last two bits in the 16-bit cycle are zero. the deserializer out- put clock period has the same variation as the serializer outputs. turn-around functionality the device passes and invert s the diri signal through the device asynchronously to the diro signal. care must be taken by the system designer to ensure that no contention occurs between the deserializer outputs and the other devices on this port. optimally the peripheral device driving the serializer should be put into a high- impedance state prior to the diri signal being asserted. when a device with dedicated data outputs turns from a deserializer to a serializer, the dedicated outputs remain at the last logical value asserted. this value only changes if the device is once again turned into a deseri- alizer and the values are overwritten. power-down mode mode 0 is used for powering down and resetting the device. when both of the mode signals are driven to a low state, the pll and refere nces are disabled, differ- ential input buffers are shut off, differential output buffers are placed into a high-imp edance state, lvcmos out- puts are placed into a hi gh-impedance state, lvcmos inputs are driven to a valid level internally, and all internal circuitry are reset. the loss of ckref state is also enabled to ensure that the pl l only powers up if there is a valid ckref signal. in a typical application mode, signals of the device do not change other than between t he desired frequency range and the power-down mode. th is allows for system-level power-down functionality to be implemented via a single wire for a serdes pair. the s1 and s2 selection signals that have their operating mode driven to a ?logic 0? should be hardwired to gnd. the s1 and s2 signals that have their operating mode driven to a ?logic 1? should be connected to a system-l evel power-down signal. table 1. control logic circuitry mode number pllx_sel s2 s1 diri description 0 x 0 0 x power-down mode 1 1 0 1 1 12-bit serializer, standard clocking, 20mhz to 40mhz ckref 0 0 1 1 12-bit serializer, over-clocked pll, 19mhz to 38.2mhz ckref x 0 1 0 12-bit deserializer 2 1 1 0 1 12-bit serializer, standard clocking, 5mhz to 14mhz ckref 0 1 0 1 12-bit serializer, over-clocke d pll, 4.7mhz to 13.3mhz ckref x 1 0 0 12-bit deserializer 3 1 1 1 1 12-bit serializer, standard clocking, 8mhz to 28mhz ckref 0 1 1 1 12-bit serializer, over-clo cked pll, 9.5mhz to 26.7mhz ckref x 1 1 0 12-bit deserializer
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 5 serializer operation mode the serializer configurations are described in the following sections. the basic serializatio n circuitry works similarly in these modes, but the actual data and clock streams differ , dependent on whether ckref is the same as the strobe signal. when it is stated that ckref = strobe, the ckref and strobe signals have an identical frequency of operation, but may or may not be phase aligned. when it is stated that ckref does not equal strobe, each signal is distinct and ckref must be running at a frequency high enough to avoid any loss of data condition. ckref must never be a lower frequency than strobe. the pll must receive a stable ckref signal to achieve lock prior to any valid data being sent. during the pll phase, strobe should not be connected to the ckref signal. once the pll is stable and locked, the device can begin to capture and serialize data. data is captured on the rising edge of the strobe signal and serialized. the serialized data stream is synchronized and sent source synchronously with a bit clock with an embedded word boundary . when operating in this mode, the internal deserializer circuitry is disabled , including the ds input buffer. the cksi serial inputs remain active to allow the pass through of the cksi signal to the ckp output. for more on this mode, please see the section on passing a word clock. if this mode is not needed, the cksi inputs can either be driven to valid levels or left to float. for lowest power operation, let the cksi inputs float. figure 3. serializer timi ng diagram (ckref = strobe) if the same signal is not used for ckref and strobe, the ckref signal must be run at a higher frequency than the stro be rate to serialize the data correctly. the actual serial transfer rate remains at 14 times the ckref frequency. a data value of zero is sent when no valid data is present in the serial bit stream. the operation of the serializer otherwise remains the same. the exact frequency that the reference clock needs is dependent upon the stabil- ity of the ckref and strobe signal. if the source of the ckref signal imple- ments spread spectrum technology, the minimum frequency of this spread spectrum clock should be used in calculating the ratio of strobe frequency to the ckref frequency. similarly if the strobe signal has significant cycle-to- cycle variation, the maximum cycle-to-cycle time needs to be factored into the selection of the ckref frequency. figure 4. serializer timing diagram (ckref does not = strobe) word n-1 word n-2 word n-1 word n dp[1:12] ckref/strobe dso ckso b 12 b 13 b 14 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 13 b 14 b 1 b 2 b 3 b 8 b 9 b 10 b 11 b 12 word n+1 word n no data word n-1 word n dp[1:12] strobe dso word n? word n word n+1 no data ckref ckso b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 1 b 2 b 3 serializer operation: (figure 3) modes 1, 2, 3 diri = 1, ckref = strobe serializer operation: (figure 4) diri = 1, ckref does not = strobe
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 6 serializer operation mode (continued) a third method of serialization uses a fr ee-running bit clock on the cksi signal. this mode is enabled by grounding the ckref signal and driving the diri signal high. at power-up, the device is configured to accept a serialization clock from cksi. if a ckref is received, this device enab les the ckref serialization mode. the device remains in this mode even if ckref is stopped. to re-enable this mode, the device must be powered down and powered back up with ?logic 0? on ckref. figure 5. serializer ti ming diagram using prov ided bit clock (no ckref) no data word n-1 word n dp[1:12] strobe dso word n-1 word n word n+1 no data cksi ckso b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 1 b 2 b 3 serializer operation: (figure 5) diri = 1, no ckref
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 7 deserializer op eration mode the operation of the deserializer is onl y dependent upon the data received on the dsi data signal pair and the cksi clock signal pair. the following two sections describe the operation of the deserializer under two distinct serializer source conditions. references to the ckref and strobe signals refer to the signals associated with the serializer device used in generating the serial data and clock signals that are inputs to the deserializer. when operating in this mode, the internal serializer circuitry is disabled, including the parallel data input buffers. if there is a ckref signal provided, the ckso se rial clock continues to transmit bit cl ocks. when s1 and s2 are asserted low, all cmos outputs are driven low at the output of the deserializer. when the diri signal is asserted low, th e device is configured as a deserializer. data is captured on the serial port and deserializer through use of the bit clock sent with the data. the word boundary is de fined in the actual clock and data sig- nal. parallel data is generated at the time the word boundary is detected. the fall- ing edge of ckp occurs coincident with the data transition. the rising edge of ckp is generated approximately seven bit times later. when no embedded word boundary occurs, no pulse on ckp is generated and ckp remains high. figure 6. deserializer ti ming diagram (seria lizer source: ckref equals strobe) the logical operation of the deserializer remains the same if the ckref is equal in frequency to the strobe or at a hi gher frequency than the strobe. the actual serial data stream presented to t he deserializer differs because it has non- valid data bits sent between words. the duty cycle of ckp varies based on the ratio of the frequency of the ckref si gnal to the strobe signal. the frequency of the ckp signal is equal to the strobe frequency. the falling edge of ckp is coincident with data transition. the low time of the ckp signal is equal to 1/2 (seven bit times) of the ckref period. the ckp high time is equal to strobe period ? half of the ckref period. figure 7 is representative of a waveform that could be seen when ckref is not equal to strobe. if ckref is significantly faster, additional non-valid data bits occur between data words. figure 7. deserializer timi ng diagram (serializer sour ce: ckref does not = strobe) word n-1 word n+1 word n b 12 b 13 b 14 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 15 b 16 b 17 word n-2 dp[1:12] ckp cksi dsi word n word n-1 word n-1 ~7 bit times word n+1 word n b 1 b 12 b 13 b 14 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 word n-2 dp[1:12] ckp cksi dsi word n word n-1 deserializer operation: (figure 6) diri = 0 (serializer source: ckref = strobe) deserializer operation: ( figure 7 ) pwrdwn = 1 diri = 0 (serializer source: ckref does not = strobe)
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 8 embedded word clock operation the fin12ac sends and rece ives serial data source synchronously with a bit cl ock. the bit clock has been modified to create a word boundary at the end of each data word. the word boundary has been implemented by skipping a low clock pulse. this appears in the serial clock stream as three consecutive bit times where signal ckso remains high. to implement this scheme, two extra data bits are required. during the word boundary phase, the data toggles either high-then-low or low- then-high, dependent upon the last bit of the actual data word. table 2 provides some examples showing the actual data word and the data word with the word bound- ary bits added. note that a 12-bit word is extended to 14 bits during serial transmission. bit 13 and bit 14 are defined with respect to bit 12. bit 13 is always the inver- sion of bit 12 and bit 14 is the same as bit 12. this ensures that a ?0? ?1? and a ?1? ?0? transition always occurs during the embedded-word phase, where ckso is high. the serializer generates the word boundary data bits and the boundary clock condition and embeds them into the serial data stream. the deserializer looks for the end of the word boundary condition to capture and transfer the data to the parallel port. the deserializer only uses the embedded word boundary information to find and capture the data. these boundary bits are stripped prior to the word being sent out the parallel port. lvcmos data i/o the lvcmos input buffers have a nominal threshold value equal to half v ddp . the input buffers are only operational when the device is operating as a serializer. when the device is operating as a deserializer, the inputs are gated off to conserve power. the lvcmos 3-state output buffers are rated for a source / sink current of 2ma at 1.8v. the outputs are active when the diri signal is asserted low. when the diri signal is asserted high, the bi-directional lvcmos i/os are in high-z state. under purely capacitive load conditions, the output swings between gnd and v ddp . figure 8. lvcmos i/o differential i/o circuitry the fin12ac employs fsc proprietary ctl i/o technol- ogy. ctl is a low-power, low-emi differential swing i/o technology. the ctl output dr iver generates a constant output source and sink current. the ctl input receiver senses the current difference and direction from the cor- responding output buffer to which it is connected. this differs from lvds, which uses a constant current source output, but a voltage sense receiver. like lvds, an input source termination resistor is required to properly termi- nate the transmission line. the fin12ac device incorpo- rates an internal termination resistor on the cksi receiver and a gated internal termination resistor on the ds input receiver. the gated termination resistor ensures proper termination regardless of direction of data flow. the relatively great er sensitivity of the current sense receiver of ctl allows it to work at much lower current drive and a much lower voltage. during power-down mode, the differential inputs are dis- abled and powered down and the differential outputs are placed in a high-z state. ctl inputs have an inherent fail-safe capability that supports floating inputs. when the cksi input pair of the se rializer is unused, it can be left floating reliably. alter nately both of the inputs can be connected to ground. ctl inputs should never be con- nected to v dd . when the ckso output of the deserial- izer is unused, it should be allowed to float. from deserializer to serializer from control dp[n] table 2. word boundary data bits 12-bit data words 12-bit data word with word boundary hex binary hex binary fffh 1111 1111 1111b 2fffh 10 1111 1111 1111b 555h 0101 01010 0101b 1555h 01 0101 0101 0101b xxxh 0xxx xxxx xxxxb 1xxxh 01 0xxx xxxx xxxxb xxxh 1xxx xxxx xxxxb 2xxxh 10 1xxx xxxx xxxxb
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 9 figure 9. bi-dir ectional different ial i/o circuitry phase-locked loop (p ll) circuitry the ckref input signal is used to provide a reference to the pll. the pll generates internal timing signals capa- ble of transferring data at 14 times the incoming ckref signal. the output of the pll is a bit clock used to serial- ize the data. the bit clock is also sent source synchro- nously with the serial data stream. there are two ways to disable the pll. the pll can be disabled by entering the mode 0 state (s1 = s2 = 0). the pll disables immediately upon detecting a low on both the s1 and s2 signals. when any of the ot her modes are entered by asserting s1 or s2 high and by providing a ckref signal, the pll powers up and goes through a lock sequence. wait a specified number of clock cycles prior to capturing valid data into the parallel port and applying ckref to strobe. when the serdes chipset transitions from a power-down state (s1, s2 = 0.0) to a powered state (example s1, s2 = 1, 1), ckp on the deserializer transitions low for a short duration and returns high. following this, the signal level of the dese- rializer at ckp corresponds to the serializer signal levels. an alternate way of powering down the pll is by stop- ping the ckref signal either high or low. internal cir- cuitry detects the lack of tr ansitions and shuts the pll and serial i/o down. internal references are not disabled, allowing for the pll to power-up and re-lock in fewer clock cycles than when exit ing mode 0. when a transi- tion is seen on the ckref signal, the pll is reactivated. application mode diagrams modes 1, 2, 3: unidirectional data transfer figure 10. simplified block diagram for unidirectional serializer and deserializer figure 10 shows basic operation when a pair of serdes is configured in an unidirectional operation mode. master operation: 1. during power-up, the device is configured as a serializer based on the value of the diri signal. 2. the device accepts ckref_m word clock and gen- erates a bit clock with embedded word boundary. this bit clock is sent to the slave device through the ckso port. 3. the device receives parallel data on the rising edge of strobe_m. 4. the device generates and transmits serialized data on the ds signals, which is source synchronous with ckso. 5. the device generates an embedded word clock for each strobe signal. slave operation: 1. the device is configured as a deserializer at power- up based on the value of the diri signal. 2. the device accepts an embedded word boundary bit clock on cksi. 3. the device deserializes the ds data stream using the cksi input clock. 4. the device writes parallel data onto the dp_s port and generates the ckp_s only when a valid data word occurs. + + ds+ ds- gated termination (ds pins only) from serializer to deserializer from control + + + + ckref_m ckso cksi ckp_s dp[1:12]_s serializer control bit ck gen. pll master device operating as a serializer dir = ? slave device operating as a deserializer dir = ? deserializer control work ck gen serializer deserializer register register ds strobe_m dp[1:12]_m
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 10 figure 11. unidirectional 8-bit rgb in terface (10mhz to 40mhz operation) figure 12. unidirectional 8-bit yuv sensor with ma ster clock on base (10mhz to 40mhz operation) note: v dd1 does not have to equal v dd2 . ckref pixel_clk pwrdwn pixel_clk v ddp v dd1 v dd1 2.775 v dd2 v ddp v dda v dda v dds v dds baseband processor fin12ac fin12ac lcd display module strobe ckso+ ckso- diro dso+/dsi- dso-/dsi+ cksi- cksi+ cksi+ cksi- dso-/dsi+ dso+/dsi- ckso- ckso+ ckp ckref strobe ckp dp[8:1] data[7:0] data[7:0] hsync hsync vsync vsync dp[9] dp[10] dp[12:11] dp[8:1] dp[9] dp[10] dp[12:11] diri diri s1 s2 s1 s2 diro note: v dd1 does not have to equal v dd2 . ckref pixel_clk master_clk master_clk pwrdwn pixel_clk v ddp v dd1 v dd2 2.775 v dd2 v ddp v dda v dda v dds v dds baseband processor camera interface fin12ac fin12ac cmos image sensor strobe yuv[7:0] data[7:0] hsync hsync vsync vsync ckso+ ckso- diro dso+/dsi- dso-/dsi+ cksi- cksi+ cksi+ cksi- dso-/dsi+ dso+/dsi- ckso- ckso+ ckp ckref strobe ckp mode0 mode1 dp[8:1] dp[9] dp[10] dp[12:11] dp[8:1] dp[9] dp[10] dp[12:11] diri diri s1 s2 s1 s2 diro
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 11 strobe pass-through mode for some applications, it is desirable to pass a word clock across a differential signal pair in the opposite direction of serialization. the fin12ac supports this mode of operation. figure 5 in the application section illustrates how to configure the devices for this mode. the following describes how to enable this functionality. for the deserializer: 1. diri = low 2. ckref = low 3. word clock should be connected to the strobe. this passes the strobe signal out the ckso port. for the serializer: 1. connect ckso of the deserializer to cksi of the serializer. 2. cksi passes the signal to ckp. when pll-bypass mode is used, the bit clock toggles on the ckp signal. table 3. control i/o flex circuit design guidelines the serial i/o information is transmitted at a high serial rate . care must be taken implementing this serial i/o flex cable. the following best practices should be used wh en developing the flex cabling or flex pcb: keep all four differential wires the same length. allow no noisy signals over or near differential serial wir es. example: no lvcmos traces over differential wires. use only one ground plane or wire over the differential serial wires. do not run ground over top and bottom. do not place test points on differential serial wires. use differential serial wires a mini mum of 2cm away from the antenna. mode number diri diro ckso ckp mode of operation 0 x z z z power down mode: s2 = 0, s1 = 0 1, 2, 3 0 1 ckso = strobe deserializer output strobe deserializer: any active mode 1, 2, 3 1 0 serializer output bit clock cksi serializer: any active mode
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 12 absolute maximum ratings the ?absolute maximum ratings? are those values beyon d which the safety of t he device cannot be guaranteed. the device should not be operated at these limits. the pa rametric values defined in the electrical characteristics tables are not guaranteed at the abs olute maximum ratings. the ?recommended operating conditions? table defines the conditions for actual device operation. recommended operat ing conditions symbol parameter min. max. unit v dd supply voltage -0.5 +4.6 v all input/output voltage -0.5 +4.6 v lvds output short-circuit duration continuous t stg storage temperature range -65 +150 c t j maximum junction temperature +150 c t l lead temperature (soldering, 4 seconds) +260 c esd rating human body model, 1.5k , 100pf all pins >3 kv s1, s2, ckso, cksi, dso, dsi, vdda, vdds, vddp (as specified in iec61000-4-2) >15 kv symbol parameter min. max. unit v dda , v dds supply voltage 2.5 3.3 v v ddp supply voltage 1.65 3.6 v t a operating temperature -30 +70 c v dda-pp supply noise voltage 100 mvp-p
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 13 dc electrical characteristics over-supply voltage and operating temperat ure ranges, unless otherwise specified. notes : 2. typical values are given for v dd = 2.775v and t a = 25c. positive current values re fer to the current flowing into the device and negative values refer to current flowing out of pins . voltages are referenced to ground unless otherwise specified (except v od and v od ). 3. v go is the difference in device ground levels between the ctl driver and the ctl receiver. symbol parameter test conditions min. typ. (2) max. unit lvcmos i/o v ih input high voltage 0.65 x v ddp v ddp v il input low voltage gnd 0.35 x v ddp v v oh output high voltage i oh = ?2.0ma v ddp = 3.3 0.30 0.75 x v ddp v v ddp = 2.5 0.20 v ddp = 1.8 0.15 v ol output low voltage i ol = 2.0ma v ddp = 3.3 0.30 0.25 x v ddp v v ddp = 2.5 0.20 v ddp = 1.8 0.15 i in input current v in = 0v to 3.6v ?5.0 5.0 a differential i/o i odh output high source current v os = 1.0v, figure 13 ?1.75 ma i odl output low sink current v os = 1.0v, figure 13 0.950 ma i oz disabled output leakage current ckso, dso = 0v to v dds s2 = s1 = 0v 1.0 5.0 a i iz disabled input leakage current cksi, dsi = 0v to v dds s2 = s1 = 0v 1.0 5.0 a v icm input common mode range v dds = 2.775 5% v go + 0.80 v v go input voltage ground off-set relative to driver (3) see figure 14 0 v r trm cksi internal receiver termination resistor v id = 50mv, v ic = 925mv, diri = 0 | cksi + ? cksi ? | = v id 80.0 100 120 r trm cksi internal receiver termination resistor v id = 50mv, v ic = 925mv, diri = 0 | dsi + ? dsi ? | = v id 80.0 100 120
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 14 power supply currents notes : 4. the worst-case test pattern produces a maximum toggling of internal digital circuits, ctl i/o and lvcmos i/o with the pll operating at the reference frequency unless otherwi se specified. maximum power is measured at the maximum v dd values. minimum values are measured at the minimum v dd values. typical values are measured at v dd = 2.5v. symbol parameter test conditions min. typ. (4) max. unit i dda1 v dda serializer static supply current all dp and control inputs at 0v or v dd nockref, s2 = 0, s1 = 1, dir = 1 437 a i dda2 v dda deserializer static supply current all dp and control inputs at 0v or v dd nockref, s2 = 0, s1 = 1, dir = 0 528 a i dds1 v dds serializer static supply current all dp and control inputs at 0v or v dd nockref, s2 = 0, s1 = 1, dir = 1 4.4 ma i dds2 v dds deserializer static supply current all dp and control inputs at 0v or v dd nockref, s2 = 0, s1 = 1, dir = 0 5.5 ma i dd_pd v dd power-down supply current i dd_pd = i dda + i dds + i ddp s1 = s2 = 0 all inputs at gnd or v dd 1.0 a i dd_ser1 14:1 dynamic serializer power supply current (4) i dd_ser1 = i dda + i dds + i ddp ckref = strobe diri = h see figure 16 s2 = h s1 = l 5 mhz 8.5 ma 14mhz 15.0 s2 = h s1 = h 10mhz 9.5 28mhz 17.0 s2 = l s1 = h 20mhz 11.0 40mhz 17.0 i dd_des1 14:1 dynamic deserializer power supply current (4) i dd_des1 = i dda + i dds + i ddp ckref = strobe diri = l see figure 16 s2 = h s1 = l 5 mhz 6.5 ma 14mhz 7.5 s2 = h s1 = h 10mhz 7.0 28mhz 10.0 s2 = l s1 = h 20mhz 8.5 40mhz 11.5
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 15 ac electrical characteristics characteristics at recommended over-s upply voltage and operating temperatur e ranges, unless otherwise specified. symbol parameter test conditions min. typ. (5) max. unit serializer input operating conditions t tcp ckref clock period (5mhz ? 40mhz) ckref = strobe see figure 19 s2=1 s1=0 s2=1 s1=1 s2=0 s1=1 71.0 35.0 25.0 t 200 100 50.0 ns ? ref ckref frequency relative to strobe frequency ckref does not = strobe s2=1 s1=0 s2=1 s1=0 s2=0 s1=1 1.1 x f strobe 40 14 28 mhz t cpwh ckref clock high time 0.2 0.5 t t cpwl ckref clock low time 0.2 0.5 t t clkt lvcmos input transition time see figure 19 90.0 ns t spwh strobe pulse width high/low see figure 19 (t x 4)/14 (t x 12)/14 ns f max maximum serial data rate ckref x 14 s2=0 s1=1 s2=1 s1=0 s2=1 s1=1 280 70 140 540 196 392 mb/s t stc dp (n) setup to strobe diri = 1 see figure 8 (f = 5mhz) 2.5 ns t htc dp (n) hold to strobe 2.0 ns serializer ac electrical characteristics t tccd transmitter clock input to clock output delay diri = 1, a=(1/f)/14 ckref = strobe, see figure 22 23a+1.5 21a+6.5 ns t spos ckso position relative to ds see figure 25 (6) -200 200 ps pll ac electrical characteristics t tplls0 serializer phase-lock loop stabilization time see figure 21 200 s t tplld0 pll disable time loss of clock see figure 26 30.0 s t tplld1 pll power-down time see figure 27 (7) 20.0 ns deserializer ac electrical characteristics t rcop deserializer clock output (ckp out) period see figure 20 17.8 t 200 ns t rcol ckp out low time see figure 20 (rising edge strobe) serializer source strobe = ckref where a = (1/f)/14 (9) 7a?3 7a+3 ns t rcoh ckp out high time 7a?3 7a+3 ns t pdv data valid to ckp low see figure 20 (rising edge strobe) where a = (1/f)/14 (9) 7a?3 7a+3 ns t rolh output rise time (20% to 80%) c l = 5pf see figure 17 3.5 7.0 ns t rohl output fall time (80% to 20%) 3.5 7.0 ns
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 16 notes : 5. typical values are given for v dd = 2.775v and t a = 25c. positive current values refer to the current flowing into device and negative values refer to current flowing ou t of pins. voltages are referenced to ground unless otherwise specified (except v od and v od ). 6. skew is measured from either the ri sing or falling edge of ckso clock to the rising or falling edge of data (dso). signals are edge aligned. both outputs should have iden tical load conditions for this test to be valid. 7. the power-down time is a function of the ckref frequency prior to ckre f being stopped high or low and the state of the s1/s2 mode pins. the specific number of clock cycles required for the pll to be disabled va ries depen dent upon the operating mode of the device. 8. signals are transmitted from the serializer source synchrono usly. note that, in some case s, data is transmitted when the clock remains at a high state. skew should only be measured when data and clock are transitioning at the same time. total measured input skew would be a combination of output skew from the serial izer, load variations, and isi and jitter effects. 9. rising edge of ckp appears approximatel y 13 bit times after the falling edge of the ckp output. falling edge of ckp occurs approximately 8 bit times after a data transition or 6 bit times after the falling edge of ckso. variation of the data with respect to the ckp signal is due to internal propagation delay differences of the data and ckp path and propagation delay differences on the various data pins. no te that if the ckref is not equal to strobe for the serializer, the ckp signal does not maintain a 50% duty cycle.the low time of ckp remains 13 bit times. control logic timing controls notes : 10. serializer enable time includes the amount of time requir ed for internal voltage and current references to stabilize. this time is significantly less than the pll lock time and does not limit overall system startup time. capacitance symbol parameter test conditions min. typ. max. units t phl_dir , t plh_dir propagation delay diri-to-diro diri low-to-high or high-to-low 17.0 ns t plz , t phz propagation delay diri-to-dp diri low-to-high 25.0 ns t pzl , t pzh propagation delay diri-to-dp diri high-to-low 25.0 ns t plz , t phz deserializer disable time s0 or s1 to dp diri = 0, s1(2) = 0 and s2(1) = low-to-high figure 29 25.0 ns t pzl , t pzh deserializer enable time s0 or s1 to dp diri = 0, s1(2) = 0 and s2(1) = low-to-high figure 29 (10) 2.0 s t plz , t phz serializer disable time s0 or s1 to ckso, ds diri = 1, s1(2) = 0 and s2(1) = high-to-low figure 28 25.0 ns t pzl , t pzh serializer enable time s0 or s1 to ckso, ds diri = 1, s1(2) and s2(1) = low-to-high figure 28 65.0 ns symbol parameter test conditions min. typ. max. units c in capacitance of input only signals, ckref, strobe, s1, s2, diri diri = 1, s1 = 0, s2=0, v dd = 2.5v 2.0 pf c io capacitance of parallel port pins dp[1:12] diri = 1, s1 = 0, s2=0, v dd = 2.5v 2.0 pf c io-diff capacitance of differential i/o si gnals diri = 1, s2=0, s1 = 0, v dd = 2.5v 2.0 pf
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 17 ac loading and waveforms figure 13. differential ctl output dc test circuit figure 14. ctl input common mode test circuit figure 15. ?worst case? serializer test pattern figure 16. ctl output load and transition times figure 17. lvcmos output load and transition times ac loading and waveforms (continued) input ds+ ds- r l /2 r l /2 v od v os + C + C dut dut vgo 100 termination + C note: the worst case test pattern produces a maximum toggling of internal digital circuits, ctl i/o and lvcmos i/o with the pll opera ting at the reference frequency unless otherwise specified. maximum power is measured at the maximum v dd values. minimum values are measured at the minimum v dd values. typical values are measured at v dd =2.5v. t 666h 0 b 13 b 14 b 1 b 2 b 6 b 7 b 8 b 11 b 12 b 1 b 2 b 11 b 12 b 1 b 2 b 6 b 7 b 8 11 11 111 00 0 0 0 0 dp[1:12] ckref cks0- cks0+ ds+ ds- 666h 999h t tlh v diff = (ds+) C (ds-) v diff 20% 20% 80% 80% ds+ ds- 5 pf 100 + C t thl t rolh 20% dpn dpn 20% 80% 80% 5pf 1000 t rohl
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 18 figure 18. serial setup and hold time figure 19. lvcmos clock parameters setup: strobe dp[1:12] strobe t stc t htc data data dp[1:12] setup time hold time mode0 = 0 or 1, mode1 = 1, ser/des = 1 ckref t clkt 90% 90% 10% 10% 50% 50% t clkt v ih v il t tcp t cpwh t cpwl figure 20. deserializer data valid window time and clock output parameters figure 21. serializer pll lock time ckp dp[1:12] t pdv data data time diri = 0, cksi and ds are valid signals. ckref 50% 75% 50% 25% t rcop t rcoh t rcol setup: cks0 ckref s1 or s2 v dd / v dda t tpls0 note: ckref signal is free running. figure 22. serializer clock propagation delay figure 23. deserializer clock propagation delay strobe cks0- cks0+ t tccd v dd/2 v diff = 0 note: strobe = ckref cksi- cksi+ ckp t rccd v dd/2 v diff = 0
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 19 ac loading and waveforms (continued) figure 24. differential input setup and hold times figure 25. differentia l output signal skew cksi- cksi+ dsi- dsi+ t h_ds t s_ds v diff=0 v diff=0 v id /2 ckso- ckso+ dso- dso+ t spos v id / 2 v diff = 0 v diff = 0 figure 26. pll loss of clock disable time figure 27. pll power-down time cks0 ckref t tppld0 note: ckref si g nal can be stopped either hi g h or low. cks0 s1 or s2 t tppld1 figure 28. serializer enable and disable time figure 29. deserializer enable and disable times ds+,cks0+ highz dsC,cks0- s1 or s2 t plz(hz) t pzl(zh) note: ckref must be active and pll must be stable. s1 or s2 dp t plz(hz) t pzl(zh) note: if s1(2) transitioning, then s2(1) must = 0 for test to be valid.
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 20 tape and reel specification bga embossed tape dimension dimensions are in millimeters. notes : a0, b0, and k0 dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c). shipping reel dimension dimensions are in millimeters. package a 0 0.1 b 0 0.1 d 0.05 d 1 min. e 0.1 f 0.1 k 0 0.1 p 1 typ. p 0 typ. p 2 0/05 t typ. t c 0.005 w 0.3 w c typ. 3.5 x 4.5 tbd tbd 1.55 1.5 1.75 5. 5 1.1 8.0 4.0 2.0 0.3 0.07 12.0 9.3 p 1 a 0 d 1 p 0 p 2 f w e d b 0 tc w c k 0 t user direction of feed tape width dia a max. dim b min. dia c +0.5/?0.2 dia d min. dim n min. dim w1 +2.0/?0 dim w2 max. dim w3 (lsl?usl) 8 330 1.5 13.0 20.2 178 8.4 14.4 7.9 ~ 10.4 12 330 1.5 13.0 20.2 178 12.4 18.4 11.9 ~ 15.4 16 330 1.5 13.0 20.2 178 16.4 22.4 15.9 ~ 19.4 10? maximum component rotation sketch c (top view) component lateral movement typical component cavity center line 1.0mm maximum w1 measured at hub dia a max dia d min b min dia c dia n see detail aa detail aa w3 w2 max measured at hub 1.0mm maximum typical component center line 10 maximum b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 21 tape and reel specification (continued) mlp embossed tape dimension dimensions are in millimeters. notes : ao, bo, and ko dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c). shipping reel dimensions dimensions are in millimeters. package a 0 0.1 b 0 0.1 d 0.05 d 1 min. e 0.1 f 0.1 k 0 0.1 p 1 typ. p 0 typ. p 2 0/05 t typ. t c 0.005 w 0.3 w c typ. 5 x 5 5.35 5.35 1.55 1.5 1.75 5.5 1.4 8 4 2.0 0.3 0.07 12 9.3 6 x 6 6.30 6.30 1.55 1.5 1.75 5.5 1.4 8 4 2.0 0.3 0.07 12 9.3 p 1 a 0 d 1 p 0 p 2 f w e d b 0 tc w c k 0 t user direction of feed tape width dia a max. dim b min. dia c +0.5/?0.2 dia d min. dim n min. dim w1 +2.0/?0 dim w2 max. dim w3 (lsl?usl) 8 330 1.5 13 20.2 178 8.4 14.4 7.9 ~ 10.4 12 330 1.5 13 20.2 178 12.4 18.4 11.9 ~ 15.4 16 330 1.5 13 20.2 178 16.4 22.4 15.9 ~ 19.4 10? maximum component rotation sketch c (top view) component lateral movement typical component cavity center line 1.0mm maximum w1 measured at hub dia a max dia d min b min dia c dia n see detail aa detail aa w3 w2 max measured at hub 1.0mm maximum typical component center line 10 maximum b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 22 physical dimensions dimensions are in millimeter s unless otherwise noted. figure 30. pb-free 42-ball ultr a small scale ball grid array (u ss-bga), jedec mo-195, 3.5mm wide bottom view 3.50 4.50 0.5 0.5 3.0 2.5 ?0.30.05 seating plane 0.230.05 0.450.05 (0.75) (0.5) (0.35) (0.6) 0.08 c 0.10 c 0.10 c 0.890.082 1.00 max 0.210.04 (qa control value) 0.10 c c 0.15 c a b 0.05 c x42 terminal a1 corner index area 2x 2x 0.2 +0.1 -0.0 land pattern recommendation
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 23 physical dimensions (continued) dimensions are in millimeter s unless otherwise noted. figure 31. pb-free 32-terminal molded leadless package (mlp), quad, jedec mo-220, 5mm square
fin12ac serdes? low-voltage 12-bit bi-directional serializer/deseriali zer with multiple frequency ranges ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin12ac rev. 1.1.0 24

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